Educational Background
Bachelor of Technology in Computer Science and Engineering
from Indian Institute of Technology, Guwahati, Assam, India (1999)
CPI: 8.19

Experience Summary
November 2000 till today
Cisco Systems
170 W Tasman Dr, San Jose, CA, USA 95134

FornaxII: March 2002 onwards
o Led discussions with the VPN team in Franklin for understanding IPSec and SSL VPN requirements and defining packet flow for combined firewall and VPN feature set
o Reviewed HQF and helped drive Formula One QoS requirements
o Helped review Zappa project and identify components to leverage
o Evangelized structured design, programming and coding practices. Successfully convinced team to use MicroC instead of microcode, wrote coding convention document drove compliance
o Evangelized pool of threads programming model to ease design and implementation of data path modules
o Architected role of XScale processor, drove the adoption of QNX as operating system to reduce development effort, increase reliability and enforce structured coding
o Drive QNX tech leads to fix issues in memory management, provide APIs for IXP specific functions
o Designed out of band debugging interface for IXPs, drove vendors(intel and QNX) to provide components and integrate. Verified solution on Deer Island
o Design strawman packet flow for inline IDS (IPS)
o Solve performance and scaling problems in implementing IPS on a network processor. Work resulted in 5 pending patents(3 filed, 2 being filed).
o Represent firewall team in meetings with Intel IXP FAEs and influence Intel to meet our requirements
o Reviewed design of Formula 1 SSP and convinced hardware team to make crypto chip inline
o Lead design and implementation of 3 modules: network processor communication, packet classifier, Xscale software


Itasca: March 2002 onwards
o Represented firewall team in Itasca design discussions and reviews and drove Itasca platform team to meet product requirements of FornaxII, IPSec and SSL
o Proposed a design for integrating the cryptoprocessor to support IPSec and SSL
o Contributed to Itasca CDE design(specifically separate flow control for control and data paths)
o Drove Cavium to identify changes to their firmware and software to enable FIPS compliance of IPSec solution
o Led the design of the Itasca inter module packet header
o Drove requirements for Kineret FPGA
o Helped review Hawea and Kineret design and drove required modifications
o Represented firewall team in converged fastpath discussions. Contributed to design document and reviewed prototype code

VPN in Fornax: Nov 2001 to Feb 2002
I evaluated cryptoprocessors from various vendors and proposed a feature set and design for IPSec in Fornax. I broke down the project into tangible tasks which was used as a base for a project plan.

Fornax 2.1: Jun 2001 to Oct 2001
Before this I co-architected the service provider feature set for FWSMs 2nd major release with inputs from marketing and distinguished system engineers. Designed the changes to data path for the same and reviewed high level design of major modules.

Fornax 1.1: Nov 2000 to June 2001
I delivered scalable TCP/IP stack, Network processor communication stack, OSPF routing, VLAN interfaces and other features to IBM NP based FWSMs first release which is in production. Led the fixes of show-stoppers and customer found major defects in various control plane modules.

Achievements
My work at Cisco has resulted in the filing of 5 patents(3 filed, 2 in process)

June, 1999 to October 2000
Hughes Software Systems
Plot-31, Electronic City, Sector 18, Gurgaon, Haryana, India - 122015

Worked with a team of around 20 people on the design and development of an operations and maintainence center for the satellite base station of a satellite-based global mobile telecom network. Prominent features I worked on were performance management, high availability, fault management, alarm simulation and OMC security.

May 1998 to June 1998
Tata Infotech Research Group
Indian Institute of Technology, Powai, Mumbai, India

Worked on a compiler optimization project sponsored by Sun Microsystems Inc. I designed a GUI editor to view and edit machine description files used by the GNU C-Compiler (gcc).

May 1997 to June 1997
Tata Research, Design and Development Centre
Hadapsar Industrial Estate, Pune, India

Worked with the development team of ADEX (a tool for repository maintenance). Designed and implemented a code generator (using inhouse tools) for generating code to convert databases from CDIF to CDIF2 format, given a metamodel for the database.

Other Achievements
Received numerous individual and team awards at Cisco and Hughes.
Won the best paper award at CYBERIA 97 organised by the Mysore chapter of IEEE.
I was the founding executive board member and treasurer of Computer Science and Engineering Association at IIT Guwahati and was actively involved in organising seminars and workshops.